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| DRAM MODULE KMM53216000BK/BKG Fast Page Mode 16M x 32 DRAM SIMM Using 16Mx4, 4K Refresh, 5V GENERAL DESCRIPTION The Samsung KMM53216000B is a 16Mx32bits Dynamic RAM high density memory module. The Samsung KMM53216000B consists of eight CMOS 16Mx4bits DRAMs in SOJ packages mounted on a 72-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM53216000B is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. KMM53216000BK/BKG FEATURES * Part Identification - KMM53216000BK(4K cycles/64ms Ref, SOJ, Solder) - KMM53216000BKG(4K cycles/64ms Ref, SOJ, Gold) * Fast Page Mode Operation * CAS-before-RAS & Hidden Refresh capability * RAS-only refresh capability * TTL compatible inputs and outputs * Single +5V10% power supply * JEDEC standard PDpin & pinout PERFORMANCE RANGE Speed -5 -6 tRAC 50ns 60ns tCAC 13ns 15ns tRC 90ns 110ns tPC 35ns 40ns * PCB : Height(1250mil), double sided component PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 Vcc A8 A9 NC RAS2 NC NC Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol NC NC Vss CAS0 CAS2 CAS3 CAS1 RAS0 NC NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss PIN NAMES Pin Name A0 - A11 DQ0-7, DQ9-16 DQ18-25, DQ27-34 W RAS0, RAS2 CAS0 - CAS3 PD1 -PD4 Vcc Vss NC Function Address Inputs Data In/Out Read/Write Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5V) Ground No Connection PRESENCE DETECT PINS (Optional) Pin PD1 PD2 PD3 PD4 50NS Vss NC Vss Vss 60NS Vss NC NC NC SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. DRAM MODULE FUNCTIONAL BLOCK DIAGRAM KMM53216000BK/BKG CAS0 RAS0 DQ1 CAS DQ2 U0 RAS DQ3 OE W A0-A11 DQ4 DQ1 CAS DQ2 U1 RAS DQ3 OE W A0-A11 DQ4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CAS1 DQ1 CAS DQ2 U2 RAS DQ3 OE W A0-A11 DQ4 DQ1 CAS DQ2 U3 RAS DQ3 OE W A0-A11 DQ4 DQ1 CAS DQ2 U4 RAS DQ3 OE W A0-A11 DQ4 DQ1 CAS DQ2 U5 RAS DQ3 OE W A0-A11 DQ4 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 CAS2 RAS2 CAS3 DQ1 CAS DQ2 U6 RAS DQ3 OE W A0-A11 DQ4 DQ1 CAS DQ2 U7 RAS DQ3 OE W A0-A11 DQ4 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 W A0-A11 Vcc 0.1 or 0.22uF Capacitor for each DRAM Vss To all DRAMs DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg Pd IOS KMM53216000BK/BKG Rating -1 to +7.0 -1 to +7.0 -55 to +125 8 50 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0*2 Typ 5.0 0 Max 5.5 0 VCC*1 0.8 Unit V V V V *1 : VCC+2.0V at pulse width 20ns, which is measured at VCC. *2 : -2.0V at pulse width 20ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM53216000BK/BKG Min - Max 960 880 16 960 880 560 480 8 960 880 10 5 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V -10 -5 2.4 - ICC1 : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 : RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min) ICC4 : Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6 : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min) I(IL) : Input Leakage Current (Any input 0VINVcc+0.5V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUTVcc) VOH : Output High Voltage Level (IOH = -5mA) VOL : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one Fast page mode cycle time, tPC. DRAM MODULE CAPACITANCE (TA = 25C, VCC=5V, f = 1MHz) Item Input capacitance[A0-A11] Input capacitance[W] Input capacitance[RAS0, RAS2] Input capacitance[CAS0 - CAS3] Input/Output capacitance[DQ0-7, 9-16,18-25, 27-34] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min - KMM53216000BK/BKG Max 50 66 38 24 17 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF Parameter Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referenced to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Refresh period Write command set-up time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Symbol -5 Min 90 50 13 25 0 0 1 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 15 13 0 10 64 0 5 10 5 30 0 5 10 5 35 10K 37 25 10K 13 50 0 0 1 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 0 10 64 10K 45 30 10K 15 50 Max Min 110 60 15 30 -6 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns 3 7 9 9 8 8 4 10 3,4,10 3,4,5 3,10 3 6 2 Note tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCPA DRAM MODULE AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF Parameter Fast page mode cycle time CAS precharge time(Fast page cycle) RAS pulse width(Fast page cycle) W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Symbol -5 Min 35 10 50 10 10 200K Max KMM53216000BK/BKG -6 Min 40 10 60 10 10 200K Max Unit ns ns ns ns ns Note tPC tCP tRASP tWRP tWRH NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 8. Either tRCH or tRRH must be satisfied for a read cycle. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. DRAM MODULE READ CYCLE KMM53216000BK/BKG tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tOFF tAA tOEZ tOEA tCAC OE VIH VIL - DQ VOH VOL - tRAC OPEN tCLZ DATA-OUT Dont care Undefined DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM53216000BK/BKG tRAS RAS VIH VIL - tRC tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN KMM53216000BK/BKG tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR tRAH tASC A VIH VIL - ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ VIH VIL - Dont care Undefined DRAM MODULE READ - MODIFY - WRTIE CYCLE KMM53216000BK/BKG tRWC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tCAH tCSH tASR VIH VIL - tASC COLUMN ADDRESS A ROW ADDR tAWD tCWD W VIH VIL - tRWL tCWL tWP OE VIH VIL - tRWD tOEA tCLZ tCAC tAA tOED tOEZ VALID DATA-OUT tDS tDH DQ VI/OH VI/OL - tRAC VALID DATA-IN Dont care Undefined DRAM MODULE FAST PAGE READ CYCLE NOTE : DOUT = OPEN KMM53216000BK/BKG tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCSH tCAH COLUMN ADDRESS tCP tCAS o tCP tRSH tCAS tASR A VIH VIL ROW ADDR tRAH tASC tCAH o o tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tRCS o tRCS tRCH tCAC tOEA OE VIH VIL - tCAC tOEA o o tCAC tOEA tAA tRAC tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ VALID DATA-OUT tOFF tOEZ DQ VOH VOL - Dont care Undefined DRAM MODULE FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM53216000BK/BKG tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCP tPC tCP tCAS o tRSH tCAS tASR A VIH VIL - tRAH tCSH tCAH COLUMN ADDRESS tASC tCAH o o tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWP tCWL tWCS tWP tWCH o tWCS tWCH tWP tCWL tRWL tCWL o o OE VIH VIL - tDS DQ VIH VIL - tDH tDS tDH o tDS tDH VALID DATA-IN VALID DATA-IN o VALID DATA-IN Dont care Undefined DRAM MODULE FAST PAGE READ - MODIFY - WRITE CYCLE KMM53216000BK/BKG tRASP RAS VIH VIL - tRP tCSH tRCD tRSH tCP tCAS tRAD tRAH tASR tASC COL. ADDR tCRP tCAS tPRWC CAS VIH VIL - tCAH tRAL tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tRWL tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tCWD tAWD tCPWD tOEA tCAC tAA tOEZ tOED tDH tDS tCWL tWP OE VIH VIL - tRAC DQ VI/OH VI/OL - tCLZ VALID DATA-OUT tCLZ VALID DATA-IN VALID DATA-OUT VALID DATA-IN Dont care Undefined DRAM MODULE RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC KMM53216000BK/BKG tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRPC tCRP tASR A VIH VIL ROW ADDR tRAH CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Dont care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWRP tWRH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM53216000BK/BKG tRC tRAS RAS VIH VIL - tRC tRP tRAS tRP tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tRCS W VIH VIL - tRRH tWRP tAA OE VIH VIL - tOEA tCAC tRAC tCLZ tOEZ DATA-OUT tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN KMM53216000BK/BKG tRC RAS VIH VIL - tRC tRP tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRAD tRSH tCHR tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tWRP W VIH VIL - tWCS tWP tWCH OE VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE KMM53216000BK/BKG tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W VIH VIL VIH VIL VOH VOL - tWRP tWRH tAA tRCS tCAC tRRH tRCH OE tCLZ tOEA tOEZ DATA-OUT tOFF DQ WRITE CYCLE W VIH VIL VIH VIL - tWRP tWRH tCWL tWCS tRWL tWCH tWP OE tDS DQ VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tAWD tRCS tCAC tAA tOEA tCWD tWP tCWL tRWL OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Dont care NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. Undefined DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care KMM53216000BK/BKG tRP RAS VIH VIL - tRASS tRPS tRPC tCHS tRPC tCP CAS VIH VIL - tCSR tOFF DQ VOH VOL - OPEN tWRP tWRH W VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Dont care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWTS tWTH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE PACKAGE DIMENSIONS KMM53216000BK/BKG Units : Inches (millimeters) 4.250(107.95) 3.984(101.19) .133(3.38) R.062(1.57) .125 DIA.002(3.18.051) .400(10.16) 1.250(31.75) .250(6.35) .080(2.03) .250(6.35) .250(6.35) 3.750(95.25) R.062.004(R1.57.10) .125(3.17) MIN ( Front view ) .350(8.89) MAX ( Back view ) .054(1.37) .047(1.19) Gold/Solder Plating Lead .010(.25)MAX .100(2.54) MIN .050(1.27) .041.004(1.04.10) Tolerances : .005(.13) unless otherwise specified NOTE : The used device is 16Mx4 DRAM, SOJ DRAM Part No. : KMM53216000BK/BKG -- KM44C16100BK |
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